I decided to start from the slave module - it has connections to cells, and measurement and balancing circuitry is the most interesting. Master module will look (electrically) as more-less standard microcontroller controller with its interfaces, will look at it after slave one is completed.

 

The slave PCB as attached to the 3P8S stack. Because it is bolted to its side and the PCB size is close to the cell size, the same PCB serves all three stack types - 3P8S, 3P11S and 3P16S. Smart.

 

 

Another photo of slave PCB. This OCB is double sided. The cells interface may seem complex, lots of parts, but I'll make judgment once the schematic is reconstructed.

 

Entire PCB is conformal coated by silicone compound that remains flexible. It also is quite poor heat conductor. That protects the circuit from outside heat. Selective coating process is used here - you can see no coated areas around mounting screws.

 

Doe 3P8S modules the PCBs are about half populated. This proved to be convenient as I can see the traces under unpopulated components which facilitates layout reconstruction.

 

The PCBs are 4 layer, with PWR and GND planes only under CPU section. The copper traces on (and in) the rest of the board are easy to see with strong source of the light.

 

The CAD software I use for reverse engineering type of projects such as this one is CIRCAD by Holophase. Besides regular schematic capture and layout generation, this software has very powerful graphics and imaging manipulation functions meant for the job. Above is fragment of the PCB and submenus related to the image processing. No matter if the image of the PCB is obtained by scanning of the PCB on the flatbed scanner or after taking a photo of it, you can reshape the image even if it is very distorted.

So the way schematic reconstruction works is as follows: you import the image of your physical circuit board into the layout software, scale it to the actual size and start drawing regular features (pads, vias, traces) right over the optical image following actual features. Once this is done, a netlist of scanned connections is generated and imported into schematic capture part of the software - the process reversed compared to "normal" flow. Provided, the component packages placed over physical images from the library have associated schematic symbols (which is always the case), an electrical schematic gets generated according to all the physical connections on the actual PCB. Now all you have to do is to drag all the component symbols on the schematic to their logical places, usually loosely following their physical locations, and after drawing interconnects following rubber-banded ratsnest liens, clear schematic will emerge.

This process is described below in greater detail. It is fun to watch schematic emerging from the ratsnest and very educational - one can learn a lot from a design worthy exploring. Granted, some hardware tools will be required to identify and measure components on the PCB. This is trivial for passive components and discrete semiconductors, and can be harder for ICs. In my case one of the ICs had obscure marking and the only way to identify what it is is to reconstruct the schematic around it and see what function it may carry. Will get to that, let's get started.

 

First, high resolution photos were taken of all the PCBs I wanted to reverse engineer. Flatbed scanner worked well for uncoated board (Main PCB), but slave's surface was too reflective and produced too much glare. It would be workable, but just a photo with digital camera produces far better result, as shown above (the image was reduced for the web page, it is actually looks far better).

 

Once the image of the PCB was imported, straightened and scaled to actual size in CAD coordinates, I started from pads and vias overlaying their actual locations. This is back side of the PCB, so all silk screen marking is X-mirrored.

 

Once vias and through holes are in right locations, I placed PCB components over their physical locations on the background photo. Then I could start drawing traces over actual copper tracks. On this photo beginning of the process is captured. POsitioning of the components does not have to be precise - as long as the traces interconnect right pads, a valid netlist will get generated which is the whole point of the exersize.

This is the fragment of the routing in progress on the back side of the board.

 

The process will take time, but eventually all the traces physically present on the PCB will be drawn on the layout. On this capture fragment of the PCB with completed traces on the top layer is shown. Note that test pads meant for electrical testing after assembly are not drawn. One difficulty doing this is that conformal coating is not very clear optically and silicone surface is quite prone to the contamination - being good insulator it accumulates electrostatic charge and attracts all kinds of debris that stick to the board. Nevertheless, this process has to be completed preferably with no errors.

 

Once done, underlying image can be removed. Here is what's left on top layer.

 

Here is the same fragment of the PCB wit hall the layers enabled. Some traces are running on inner layers, they are represented by different color. At this point it makes sense to measure and identify as many components as possible as their types and values will be translated by netlist processor that expects the input.

 

I traced ground signal from the CPU power supply all the way to the interface connector at the edge, but for the life of me just could not see the trace or traces connecting them. So I fed the path with rectangular wave signal from a function generator and whiped out my trusty positional current probe that can trace PCB tracks through the fiber. Running the probe tip across the PCB from top to bottom identified the ground trace carrying my test signal in about 15 seconds. Interestingly, turns out this is regular width signal track.

 

Another handy little gadget was component identifier. Marking on SMT discrete components tells you pretty much nothing and garden variety of components is packaged into identical packages such as SOT23 pictured above. These three photos show examples of test of different components unsoldered from the BMS PCB, whose leads were extended with bare wires. The identifier shows FETs, bi-polar transistors, regular and Schottky diodes, LEDs, etc. It cannot differentiate components with working voltage above its 9V battery, such as Zener diodes or TVS'es, but once you see those placed on the schematic you can have pretty good guess.

 

The values of resistors can be directly read off their marking, but SMT caps are never marked. These smart tweezers (LCR meter) is all I needed.

So from this point on schematic reconstruction is a tedious but straight forward process of moving components around and interconnecting them neatly with a "wire" in the schematic capture tool, so the ratsnest link between points being connected disappears. Once all the ratsnest is gone, PCB's electrical schematic diagram with all the component values will emerge. Click on "Schematic" link on the left banner to see how this works in more detail.