Here is the fragment of the circuit representing isolated CAN interface. the PCB section looks like this:

 

The circuit consists of the ADuM1301 - AD's digital isolator, the Fairchild's 74HCT00 quad 2-inpit NAND gates, the LM7805 voltage regulator and the classic PhilipsTJA1050 CAN transceiver. This part gives away how old the design is, more on this later. For now we'll focus on the process of converting this into the schematic.

All the tracks are laid down over the image.

 


Image removed, components identified, and the netlist processor assigned signal names to tracks and pads.

 

After importing complete netlist all the components are lined up at the bottom of the schematic and nets are interconnected by the ratsnest. Because location of components is defined by the sequence it was scanned by the netlist processor, the nest of course looks like a mess. However, it is easy to group components that belong to one logical section of the schematic. For instance, based on the layout, I need to find U1, C6, U4, D1, D2 etc. - components representing CAN interface, and drag them away from the mail cluster positioning in about the places on the schematic sheet where one would expect them to be. This is iterative process, but with experience and after looking at hundreds of such interfaces (let alone designing them), I can envision what the schematic is going to look like by just looking what type of components is used. In A123's case they've used ADuM301. This is digital isolator transmitting data between CPU and CAN transceiver. It is needed because CPI is at the potential of the lithium cells (can be hundreds of volts above ground level) and the CAN bus is normally near chassis ground (reference of vehicle's CL15 circuit e.g. 0V potential of 12V net). Because some quirks in the design of the TJA1050, glue logic assuring right dominant and recessive state on the inputs of the transceiver is used. So I have to position logic gates near the transceiver symbol. Finally, output is obviously protected by TVS'es, very standard practice and it is well visible on the PCB. So D1 and D2 positioned between CANH and CANL I/Os of the TJA1050 and the interface connector. There is also voltage regulator for the isolated section of the interface, its position is not critical. I'll put it in the empty spot next to the TJA1050. In a first iteration arrangement will look like this:

Initial location of the schematic symbols with references matching PCB components.

Then re-running the ratsnest generation yields the following:

From here it is easy to see what the final schematic will look like. Replacing ratsnest lines with neatly laid "wire" lines produces near final schematic:

 

Values of some caps are still missing, but it's OK for now - it will be only a matter of editing component on the POCB after actual measurement and re-running the netlist. All the values on the schematic will be automatically updated and appear here.

So what can I tell about this interface? This is very classic way of doing it, but today we have better components to implement the same function. For instance ISO1050 which is modern version of the TJA1050 is already isolated transceiver - this eliminates the need for expensive ADuM1301. The second channel of ADuM1301 (pin 4 input, pin 132 output) is used to place the TJA1050 in listen only (stand-by) mode. This adds reliability in this automotive application since the transceiver can also be placed in off-bus mode if something goes wrong with the CPU and its output that feeds ADuM1301's pin 4, goes low or high-Z state. In this case R5 pull-down asserts logic zero on pin 4 which gets transmitted to the pin 13 and further to the pin 10 of logic gate U5c. The output of U5c connected to "s" (stand-by) input of the TJA1050 receives logic 1, and the transceiver goes off-bus. The gate U5d is unused. Small caps  C17 and C18 control slope of the output signal while transitioning from CANL to CANH and back, greatly reducing EMI. D1 and D2 TVS'es (typically 35 to 40 VDC) protect transceiver from transients on the bus. The circuit is fed with +12V to the regulator whose output supplies power to the U5 and U1.

Connections to pins 3, 4 and 5 of the ADuM1301 are not visible here, but they go directly to the CPU IOs  RF1, RF0 and RC2. The CPU used in slave PCB is dsPIC30F6011. I was delighted to discover this as I've used this exact chip for one of my BMS projects, circa 2009. Evidently A123's engineer who design this circuit and I thought alike and made identical judgment of the processing power required to handle about 6-8 cells.

Moving on to the balancing circuit

What emerges so far is passive balancers for individual cells. The cell loads consist of 8 paralleled 91 Ohm 1206 size SMT resistors rated at 0.25W power dissipation. We can already make some observations, quick calculations and conclusions. First, the load spread over large PCB area than if one fixed high power resistor is used which may get quite hot unless large and heavy. Aside cheaper solution, it is more reliable as failure of one resistor will not cause failure of the balancing load. Also, all the components are SMT allowing simpler automated assembly.

The nominal voltage of the AMP20M1HD-A cell is 3.3VDC. 8 paralleled 91 Ohm resistors electrically are single 11 375 Ohm 2W resistor. This means designed balancing current is 3.3/11.375=0.29A or 290mA, probably 300 mA near top voltage. Max dissipated power is just shy of 1W. What is interesting about the balance circuit arrangement above is that the most bottom cell is controlled by Nch FET and "power resistor" is directly connected to the positive terminal, but for all other cells this is flipped up side down - the loads are controlled by Pch FET and respective resistors are connected to the negative terminal of their cell. Without seeing the rest of the schematic it is hard to tell why is there such a non-uniform connection, but obviously this has to do with limitation of the most bottom cell's connection. Will figure this out once the rest of the schematic get reconstructed.

To be continued...